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A total of 75 records were found in 0.313 seconds
Alternative Architectures for the 2-D DCT Algorithm
ISCAS, 2156-2159, 1995
A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation
ISCAS, 1992-1995, 1995
Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors
ISCAS, 79-82, 1994
Methodology for the Design of Signed-digit DSP Processors
ISCAS, 1833-1836, 1993
Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems
ISCAS, 1821-1824, 1993