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A total of 100 records were found in 0.438 seconds
Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings
ISBN: 3-540-29105-93725, 2005
Proving the Correctness of Pipelined Micro-Architectures
MBMV, 89-98, 2000
Making the Original Scoreboard Mechanism Deadlock Free
ISTCS, 92-99, 1996
High Performance Transaction Systems on the SB-PRAM
ISTCS, 1-10, 1995
Applications of PRAMs in Telecommunications
IFIP Congress (1), 203-210, 1994
Scheduling Vector Straight Line Code on Vector Processors
Code Generation, 73-91, 1991
Überblick über PRAM-Simulationen und ihre Realisierbarkeit
Entwurf und Betrieb verteilter Systeme, 15-39, 1990
Parallelrechner aus wissenschaftlicher und kommerzieller Sicht
ARCS, 139-145, 1990
Contributions of Theoretical Computer Science, Applied Computer Science and Numerical Mathematics to the Design of Parallel Computers
IFIP Congress, 459-460, 1989
Innovative Informations-Infrastrukturen, Ergebnisse einer Kooperation der Universität des Saarlandes und der Siemens AG, I.I.I.-Forum, Saarbrücken, 12.-13. Oktober 1988, Proceedings
ISBN: 3-540-50334-X184, 1988
Parallel Computation on 2-3-Trees
ITA, 17(4):397-404, 1983
Effizienz Paralleler Rechner
GI Jahrestagung, 54-64, 1980
Kolmogorov complexity and lower bounds
FCT, 325-334, 1979